1. Field of the Invention
This invention relates to simplifying the equalizer needed to combat the intersymbol interference present in a digital communication system.
2. Background
The dramatic increase in desktop computing power driven by intranet-based operations and the increased demand for time-sensitive delivery between users has spurred development of high speed Ethernet LANs. 100BASE-TX Ethernet, using category-5 copper wire, and the newly developing 1000BASE-T Ethernet for Gigabit/s transfer of data over existing category-5 copper wire require new techniques in high speed symbol processing. Gigabit per second transfer can be accomplished utilizing four twisted pairs and a 125 megasymbol/s transfer rate on each pair where each symbol represents two bits. Twisted pair copper cables are also used in wide-area networking (WAN) and digital subscriber loop data communication applications. With ever increasing need for bandwidth, technologies that support high data transfer rates across twisted pair cables are gaining wide acceptance. 100Base-TX (fast Ethernet), 1000Base-T transmission over long haul copper (also known as Gigabit Ethernet) and digital subscriber loop technologies all transmit data at high transmission rates over twisted copper pairs.
Physically, data is transferred using a set of voltages where each voltage represents one or more bits of data. Each voltage in the set of voltages is referred to as a symbol and the whole set of voltages is referred to as a symbol alphabet.
One system of transferring data at high rates is Non Return to Zero (NRZ) signaling. In NRZ signaling, the symbol alphabet {A} is {xe2x88x921, +1}. A logical xe2x80x9c1xe2x80x9d is transmitted as a positive voltage while a logical xe2x80x9c0xe2x80x9d is transmitted as a negative voltage. At 125 M symbols/s, the pulse width of each symbol (i.e. the positive or negative voltage) is 8 ns.
Another system for high speed symbol data transfer is referred to as MLT3 signaling and involves a three voltage level system. (See American National Standard Information system, Fibre Distributed Data Interface (FDDI)xe2x80x94Part: Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD), ANSI X3.263:199X). The symbol alphabet for MLT3 is {A}={xe2x88x921, 0, +1}, corresponding to the set of voltages {xe2x88x92V, 0, V}. The voltage V is typically 1 V.
In MLT3 transmission, a logical xe2x80x9c1xe2x80x9d is transmitted by either a xe2x88x921 or a +1 symbol while a logic xe2x80x9c0xe2x80x9d is transmitted as a 0 symbol. A transmission of two consecutive logic xe2x80x9c1xe2x80x9ds does not require the system to pass through zero in-the transition. A transmission of the logical sequence (xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d) would result in transmission of the symbols (+1, 0, xe2x88x921) or (xe2x88x921, 0, +1) depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence was a +1, then the symbols (+1, 0, xe2x88x921) are transmitted. If the symbol transmitted before this sequence was a xe2x88x921, then the symbols (xe2x88x921, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence was a 0, then the first symbol of the sequence transmitted will be a +1 if the previous logical xe2x80x9c1xe2x80x9d was transmitted as a xe2x88x921 and will be a xe2x88x921 if the previous logical xe2x80x9c1xe2x80x9d was transmitted as a +1.
In the ideal MLT3 system, the transmit driver simply sends a voltage pulse corresponding to the symbol being transmitted. The pulse is of duration 8 nanoseconds for each one of the transmit symbols and has a finite rise/fall time of three to five nanoseconds (See American National Standard Information system, Fibre Distributed Data Interface (FDDI)xe2x80x94Part: Token Ring Twisted Pair Physical Layer Medium Dependent (TP-PMD), ANSI X3.263:199X).
The detection system in the MLT3 standard, however, needs to distinguish between three voltage levels, instead of two voltage levels in a two level system. The signal to noise ratio required to achieve a particular bit error rate is higher for MLT3 signaling than for two level systems. The advantage of the MLT3 system is that the power spectrum of the emitted radiation from the MLT3 system is concentrated at lower frequencies and therefore more easily meets FCC radiation emission standards for transmission over twisted pair cables. Other communication systems may use a symbol alphabet having more than two voltage levels in the physical layer in order to transmit multiple bits of data using each individual symbol.
A block diagram of a typical digital communication transmission system is illustrated in FIG. 1. In FIG. 1, the transmitted data is represented by the symbol sequence {ak}. The transmitted symbols in the sequence {ak} are members of the symbol alphabet {A}. In the case of three level MLT3 signaling, the symbol alphabet {A} is given by {xe2x88x921, 0, +1}. The index k represents the time index for that symbol, i.e., at sample time k, the symbol being transmitted is given by ak. The channel response is represented by the channel transfer function f(z). The channel function f(z) is the Z-transformation of the sampled time response of the channel.
In FIG. 1, the transmitted symbols {ak} enter the channel 1. The signal output from the channel 1, xk, is a linear distortion of the transmitted symbols {ak}, the distortion being described by the channel transfer function f(z). The signal xk is summed in adder 2 with a noise sample nk to form the signal yk. The noise samples {nk} represent the random noise on the transmission line. The signal yk, suffering from both the channel distortion and the random noise, is then input to the detector 3. Detector 3 inputs the distorted signals yk, counteracts the effects described by the channel transfer function f(z), and outputs a sequence of detected symbols {xc3xa2k}.
FIG. 2 shows a typical 100Base-Tx transmitter. The transmit data path in a 100Base-TX transceiver (IEEE 802.3u Standard) consists of a physical coding sub-layer (PCS) 11, and a physical medium dependent (PMD) sub-layer 12. The PCS 11 contains a medium independent interface (MII) 4 and a 4B5B (rate 4/5) encoder 5. The medium independent interface 4 is the interface between the transceiver and the media access controller (MAC). The 4B5B encoder 5 guarantees sufficient transitions in the transmit data for the purpose of robust clock recovery in the receiver and generates Ethernet control characters. The data rate at the output terminal of the PCS 11 is 125 Mhz due to the rate penalty associated with the 4B5B encoder 5. The physical medium dependent portion 12 of the 100Base-TX transmit data path consists of a scrambler 6, binary to MLT3 converter 7, and a transmit driver 8 which outputs a 1V peak-to-peak signal onto the twisted pair 10 through an isolation transformer 9. The transmit symbol sequence {ak} is generated in the binary to MLT3 converter 7.
It is assumed that the channel model represented by f(z) includes the effect of transmit and receive filtering. In addition, the transmission channel is assumed to be linear in that two overlapping signals simply add as a linear superposition. Therefore, the channel transfer function polynomial can be defined as
f(Z)=f0+f1Zxe2x88x921+f2Zxe2x88x922+ . . . +fNZxe2x88x92N,xe2x80x83xe2x80x83(1)
where f0, . . . , fj, . . . , fN are the polynomial coefficients. The polynomial coefficient fj represents the dispersed component of the (kxe2x88x92j)th symbol present in the kth received sample and N is a cut-off integer such that fj for j greater than N is negligible. The polynomial f(Z) represents the Z-transformation of the sampled frequency response of the transmission channel. In Equation 1, Zxe2x88x921 is considered to be a one clock period delay. See A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing 1989.
The noiseless output of the channel at sample time k is then given by
xk=f0*ak+f1*akxe2x88x921+ . . . fN*akxe2x88x92N,xe2x80x83xe2x80x83(2)
where, without loss of generality, f0 can be assumed to be 1. Thus, the channel output signal at time k depends not only on transmitted data at time k, but past values of the transmitted data. This effect is known as xe2x80x9cintersymbol interferencexe2x80x9d (ISI). See E. A. Lee and D. G. Messerschmitt, Digital Communications (1988).
Intersymbol interference is a result of the dispersive nature of the communication channel. The IEEE LAN standards require that systems be capable of transmitting and receiving data through at least 100 meters of category-5 cable. FIG. 3A shows a transmission symbol stream with the effects of dispersion. FIG. 3B shows the power spectrum of the dispersed pulse versus frequency. In a 100 meter cable, the signal strength at the Nyquist frequency of 62.5 Mhz is reduced nearly 20 db at the receiving end of the cable. Given this dispersion, a single transmitted symbol may affect several received symbols at the output of the wire.
The noise element of the signal is represented by the sequence {nk}. Therefore, the noisy output signal of the channel is given by
yk=xk+nk,xe2x80x83xe2x80x83(3)
where the noise samples {nk} are assumed to be independent and identically distributed Gaussian random variables (see Lee and Messerschmitt) with variance equal to "sgr"2.
Most state-of-the art communication systems use two types of detectors for combating the ISI described by equation (2). These two detectors, Linear Equalization and Decision Feedback Equalization, are shown in FIG. 4A.
A finite impulse response linear equalizer having m+1 multipliers is illustrated in FIG. 4B. In FIG. 4B, the symbol yk is inputted to a delay array 10 having delays (D1 through Dm) which, at each stage, delay the symbol by one time period. A set of multipliers 20 having multipliers M0 through Mm multiply each of the m+1 symbols in the array of delays D1 through Dm by a corresponding coefficient C0 through Cm. The adder 30 adds together the output signals from multipliers M0-Mm to obtain the resulting signal
ak=C0yk+C1ykxe2x88x921+ . . . +Cmykxe2x88x92mxe2x80x83xe2x80x83(4)
The signal akxe2x80x2 from the linear equalizer is inputted to slicer 40 which decides on the output symbol xc3xa2k. The output symbol xc3xa2k is the symbol from the symbol alphabet {A} which best approximates the input signal ak.
The multiplier coefficients, C0 through Cm, define a transfer function T given by
T=C0+C1Zxe2x88x921+ . . . +CmZxe2x88x92m.xe2x80x83xe2x80x83(5)
The coefficients C0 through Cm may be chosen by an intelligent algorithm in an adaptive implementation in order to optimize the functioning of the equalizer. A zero-forcing linear equalizer (ZFLE) has a transfer function T given by the inverse of the frequency response of the channel. A minimum mean squared error based linear equalizer (MMSE-LE) optimizes the mean squared error between the transmitted data and the detected data, and hence finds a compromise between the un-canceled ISI of the output signal of the equalizer and the output noise variance.
FIG. 4C illustrates a typical finite impulse response Decision Feedback Equalizer (DFE) with Nff multipliers in the feed-forward filter and Nfb multipliers in the feed-back filter. The input signal yk is inputted to the feed-forward filter 100. The resulting signal from the feed-forward filter is added with the negative of the resulting signal from the feed-back filter 200 in adder 300. The added signal ak is inputted to slicer 400 which determines the output symbol xc3xa2k of the equalizer.
In feed-forward filter 100, the input signal yk is inputted to a feed-forward delay array having delays D1ff through DNffxe2x88x921ff. Each delay delays the signal by one period so that the delay array 101 stores Nffxe2x88x921 past input signals. Each of the stored signals is multiplied by a corresponding coefficient C0 through CNffxe2x88x921 by multipliers M0ff through MNffxe2x88x921ff. The output signals from the multipliers M0ff through MNffxe2x88x921ff are added together in adder 103 so that the signal inputted to adder 300 on line 301 is given by
akxe2x80x3=C0yk+C1ykxe2x88x921+ . . . +CNffxe2x88x921ykxe2x88x92Nff+1.xe2x80x83xe2x80x83(6)
The feed-back filter 200 inputs the output symbol xc3xa2k to a feed-back delay array 201 having delays D0fb through DNfbxe2x88x921fb. The feed-back delay array 201 stores Nfb past determined symbols, xc3xa2kxe2x88x92Nfb through xc3xa2kxe2x88x921. The output symbols of the feed back delay array 201 are inputted to multipliers 202, M0fb through MNfbxe2x88x921fb respectively. The resulting signals from multipliers 202 are added in adder 203 so that the input signal of adder 300 on line 302 is given by
akxe2x80x2xe2x80x3=b0xc3xa2kxe2x88x921+b1xc3xa2kxe2x88x922+bNfbxe2x88x921xc3xa2kxe2x88x92Nfb.xe2x80x83xe2x80x83(7)
Adder 300 adds the input signal on line 301 with the negative of the input signal on line 302 to obtain akxe2x80x2=akxe2x80x3xe2x88x92akxe2x80x2xe2x80x3, which is received by slicer 400. Slicer 400 decides on the output symbol xc3xa2k. The output symbol xc3xa2k arrived at by slicer 400 is the symbol in symbol alphabet {A} which most closely approximates the signal akxe2x80x2 at the input terminal of slicer 400.
The DFE operates on the principle that if the past transmitted data is correctly detected, then the ISI effect of these past data symbols can be canceled from the current received signal prior to detection. For a zero-forcing DFE, the feed-forward transfer function is set to 1 (i.e., C0=1 and C1 through Cm are 0 in the finite impulse response filter of FIG. 4C), and the feedback transfer function is given by [f(z)xe2x88x921], f(z) being the channel transfer function. Practical implementation of decision feed-back equalizers utilize finite impulse response (FIR) feed-back filters. A finite impulse response filter implements a transfer function which is finite in duration. Infinite impulse response (IIR) filters, those that implement a transfer function which is infinite in duration, have difficulty implementing algorithms for adaptively adjusting the multiplier coefficients.
Since past detected data samples contain no noise, DFE does not suffer from noise enhancement while the linear equalizer does. However, DFE suffers from error propagation; i.e., if one of the past detected symbols is incorrect, then the effects of that error propagate to more symbol decisions in the future.
Also, because the equalizer is a feedback equalizer, pipelining of the feed-back filtering operation is not possible, unlike a linear equalizer whose operation can be pipelined. In particular, a linear equalizer depends only on input signals and therefore can use several clock cycles to perform the computational functions necessary to arrive at an output signal. The effect of using several clock cycles is to enable high speed implementation of the equalizer by splitting the computational load of the equalizer over several clock cycles. A decision feedback equalizer, however, depends on the output of previous symbols to determine the current symbol, i.e., xc3xa2kxe2x88x921 is necessary to determine xc3xa2k. Therefore, all computations to determine the symbol xc3xa2k need to be accomplished within a single clock cycle, preventing pipelining of the equalizer.
Mathematically, the frequency response of the twisted pair cable can be modeled as exe2x88x92xcex2. The exponent xcex2 is xcex1l (jf)xc2xd where xcex1 is the cable coefficient, l is the length of the cable in meters, and f is the frequency in Mhz. For a category-5 twisted pair cable, xcex1 is approximately 3.7xc3x9710xe2x88x923/(m{square root over (MHz)}). The overall frequency response of the system, including the channel, the TX shaping and the transformer, is given by
H(f)=HT(f)exe2x88x92xcex2,xe2x80x83xe2x80x83(8)
where HT(f) includes the effects of transmit shaping and transformer frequency response. These effects include the effect of an analog to digital converter, a low pass filter, and a high pass filter. HT(f) can be approximately modeled by                                           H            T                    ⁡                      (            f            )                          =                                            sin              ⁢                              xe2x80x83                            ⁢              π              ⁢                              xe2x80x83                            ⁢              fT                                      π              ⁢                              xe2x80x83                            ⁢              fT                                ⁢                      1                          [                              1                +                                  j                  ⁡                                      (                                          f                      /                                              f                        H                                                              )                                                              ]                                ⁢                                    jf              /                              f                L                                                    [                              1                +                                  j                  ⁡                                      (                                          f                      /                                              f                        L                                                              )                                                              ]                                                          (        9        )            
where T=1/125 MHz, fL is of the order of 25-50 Khz, and fH is approximately 85 Mhz for the fast Ethernet transmission system.
A sampled impulse response of the channel (a folded spectrum) is given by
Hs,xcfx84(f)=(l/T)xcexa3k HT(f+k/T)exe2x88x92j2xcfx80fxcfx84xe2x80x83xe2x80x83(10)
where xe2x88x920.5/Txe2x89xa6f less than 0.5/T and xcfx84 is the timing phase of the sampler that is selected by the clock recovery circuitry in the receiver. See Lee and Messerschmitt.
A typical equalizer implements the channel function f(z) calculated by setting f(z=ej2xcfx80fT)=Hs,xcfx84(f). This process results in the design of an equalizer having 12 or more multipliers.
In accordance with the invention, an equalizer which takes advantage of the characteristics of the frequency response of the channel is presented. Applicant has observed that the frequency response of the channel is approximated by a function having a series of poles in the denominator. The number of multipliers required to implement the equalizer is equal to the number of terms in the series of poles and, therefore, is minimal.
In the preferred embodiment, a linear equalizer using only two multipliers is presented. In a second embodiment, a decision feedback equalizer utilizing only two multipliers is presented. Both equalizers exploit the observed channel function having a series of poles in the denominator.
A detector embodying this invention has an equalizer with an input terminal to receive an input signal suffering from channel distortion. The channel distortion is described by a channel function with a denominator polynomial of order L and having K denominator polynomial coefficients, L being a positive integer greater than 1 and K being a positive integer less than or equal to L. The equalizer implements a channel function with L delays and K multipliers, each of the K multipliers having a multiplier coefficient equal to a corresponding one of the K denominator polynomial coefficients. The equalizer outputs a corrected signal in response to the K denominator polynomial coefficients and the input signal.
A finite impulse response (FIR) linear equalizer implementing the denominator polynomial is the preferred embodiment of the invention. An infinite impulse response (IIR) decision feedback equalizer implementing an IIR filter in the feed-back section is presented as another embodiment of the invention.
The invention and its embodiments are further described with the figures and the accompanying discussion.